A specific MCU design of On board Unit (OBU) in Electronic Toll Collection (ETC) system is proposed in this paper. According to the ETC applications, this MCU is designed to have the minimum application system. Results show that this MCU design scheme is feasible and fulfills the requirements of the central control chip used for OBU in ETC system. The MCU has about 113,000 gates, and its area is 642.74 !-lm x 494.20 !-lm under SMIC 65nm technology. The average power consumption is 98!-lW. Compared with the general MCU, the MCU has a larger advantage in ETC application.<\/p>\n\n\n\n
With the widespread application of\nETC system, the development of OBU device becomes a hotspot of intel\u00adligent\ntransport systems [1]. Currently on the market, OBU device is realized by using\nthe method of board level circuit [2]. The device has bulky appearance, high\ncost, and is not conducive to the promotion of a wide range. As shown in Figure\n1, SOC is a viable solution to solve this shortcoming. Reader chip (13.56MHz)\n<\/p>\n\n\n\n
Soft IP core has advantages of low\ncost, free configuration, and it can be embedded into other function module.\nTherefore, IP soft core becomes the main part of SOC design [4]. ARM processor\nhas excellent performance, but its power consumption is very low and the number\nof gates used is small [5]. In this design, a 32 bit RISC processor IP core\ndesigned by ARM company is used. CHIP\nDESIGN System Design The overall design of\nthe system: The final design is applied to the OBU in ETC sys\u00adtem. The MCU is\nable to control 5.8G RF chip and 13.56M reader chip, and communicates with\nthem. ARM IP core is used as the CPU core. SPI, UART and other interfaces are designed as peripheral. The control signal\nand interrupt signal of 5.8G RF chip and 13.56M reader chip are also required.\nThe system clock is designed as 55MHz. The chip system block diagram is as\nfollows: <\/p>\n\n\n\n
Taking into ac\u00adcount the application\nand scalability of the design, the SRAM is designed as 8 k bytes. Second, the\nprogram of CPU is stored in the ROM and EFLASH. The bootloader, the interface\nused for pro\u00adgram download, the drivers of peripheral interfaces and the\ndrivers of EFLASH operation are stored in ROM. By assessing the amount of the\nprogram, the capacity of the ROM is designed as 2 K bytes. The main application\nprogram is stored in EFLASH. According to the amount of actual application\ncode, taking into account the scalability of chip design, an EFLASH with 64 k\nbytes is used in the design. Module division: The memory management unit: ROM,\nSRAM and EFLASH connect with CPU through AHB. Through the logical address, the\nCPU accesses different memory areas. So this design achieves the memory\nmanagement unit as an interface of CPU bus and memory IP to realize the ICSICT2014, Guilin, China <\/p>\n\n\n\n
function of mapping the logical\naddress to physical ad\u00address and the function of timing conversion. This design\ncan realize unified management and access, and facilitate the extension of\nmemory in the future. The interface module: In order to communicate with\nperipheral chips, two SPI masters and a SPI slave are designed. They are used\nto communicate with the 5.8G RF chip and 13.56M card reader chip. In addition,\nin order to meet the requirements of peripheral chips, a group of GPIO and 4\ninterrupt interfaces are designed. Chip needs the entrance to download program\nand other application interface, so two UART interfaces are designed to down\u00adload\nthe program and meet other application. These in\u00adterfaces are connected to CPU\nthrough APB. Clock and reset module: The chip needs a 55MHZ system clock which\nis provided by an external crystal oscillator. The design of the reset module\ncombines syn\u00adchronous reset and asynchronous reset. The reset signal after\nsynchronization is used to asynchronous reset. The clock module divides the\nsystem clock generated by ana\u00adlog circuit to produce the desired clock after\ngating, re\u00adducing the power consumption of the chip. Memory Management Unit\nDesign The memory management unit is connected with CPU and memory module. <\/p>\n\n\n\n
The CPU can access the memory via\nthe AHB bus. ROM IF, EEPROM IF, and EFLASH Controller are control modules of\nROM, RAM, and\nEFLASH. Particu\u00adlarly, EFLASH Controller also connects with the APB bus, which\nis the channel for UART interface to download the program to EFLASH. MMU <\/p>\n\n\n\n
The function of decoder is to map\nthe logical address to a physical address, and produce memory chip select\nlogic. The address assignment is shown in <\/p>\n\n\n\n
The SPI master implementation\nprocess is as follows: Generally, SPI is in sleep mode. When SPI master is in\nsending mode, CPU configures the registers of SPI master. First, CPU configures\ncontrol register, baud rate register, and byte register. Then, CPU configures\ndata register, and SPI master enters the sending state. In the sending state,\nthe data in data register is first loaded into the shift register. At the same\ntime CS signal and SCLK signal are outputted according to the baud rate register.\nFinally, the shift register is shifted, and the highest bit is outputted as\nMOSI based on the edge of SCLK. When SPI master is in receiving mode, the CS\nsignal is still valid. According to the edge of SCLK, the received data is\nloaded into shift register. Once SPI master receives a byte of data, CPU takes\nthe data away, and then SPI master continues to accept the next byte signal.\nSPI slave, UART, GPIO, and interrupt interfaces are not elaborate in this\npaper. By using clock gating tech\u00adnique, the clock signals of these modules are\npulled up when these modules are not in use. <\/p>\n","protected":false},"excerpt":{"rendered":"